1. Field of the Invention
The present invention relates to an electronic solid-state read-only memory (ROM), particularly of the CMOS type, with static operation, i.e. with no need for a timing clock.
2. Prior Art
As is known, static read-only memories in CMOS technology are essentially constituted by a certain number of metallic and polycrystalline-silicon paths arranged in the form of crossing rows and columns, the columns being connected to respective pull-up elements, which in practice are transistors which always conduct between the columns and a supply voltage, and the rows leading to a address driven decoder circuit raises a single row to a high voltage. In each crossing, the rows and the columns can be insulated or the column can be connected to the drain of a transistor (a pull-down transistor) having its source connected to the ground and its gate driven by the row. Therefore, when a given row is raised to a high voltage by the decoder, the columns which it crosses are brought to a ground voltage if the pull-down element is present, while they remain at high voltage if they are insulated. Therefore the presence of the pull-down transistor corresponds to a logical "1", while its absence corresponds to a "0".
The same structure as ROM memory is found in programmable logic arrays, or PLAs, which are distinguished by true ROM memories by the fact that in this case not all the possible combinations of input to the decoder are decoded. For the purposes of the invention, the term "read-only memory" will be used to refer both to ROM memories and to programmable logic arrays.
During the read of a given address of a ROM memory of this type, both the pull-up and the pull-down cells are activated, and a static current thus flows from the supply voltage towards ground. The read speed is therefore limited, and the current consumption is high, since each cell drains current from the supply voltage.
In order to overcome the disadvantages of low speed and high consumption of static ROM memories, it is already known to provide dynamic ROM memories, in which the steps 0.sub.1 and 0.sub.2 of the clock are used to alternately activate the pull-up cells and the pull-down cells, so as to never have static current. The charge stored during the first step provides the current for the operation of the pull-down cells on the columns. However, if the memory is operated at low speed (i.e. if the clock frequency is low), it is necessary to provide a latch at the output to statically store the status of the columns during the second step, since the dispersion current can discharge the parasite capacitor of the column.
Dynamic memory is faster than static memory and has a lower consumption, but it has the disadvantage that it requires the two clock steps 0.sub.1 and 0.sub.2, linked to the synchronism of the system, and that it furthermore requires a latch at its output.